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Dynamic Digital Twin: Diagnosis, Treatment, Prediction, and Prevention of Disease During the Life Course

A digital twin (DT), originally defined as a virtual representation of a physical asset, system, or process, is a new concept in health care. A DT in health care is not a single technology but a domain-adapted multimodal modeling approach …

A 10-bit, 771 nW Time-Mode ADC with a 2-Step TDC for Bio-Signal Acquisition

In this paper, we present the design of a low-voltage, low-power, and small-area time-mode ADC (TM-ADC) for bio-signal sensing applications. The proposed time-mode ADC (TM-ADC) consists of a programmable oversampling ratio (OSR), voltage-controlled …

A Chip Integrity Monitor for Evaluating Long-term Encapsulation Performance Within Active Flexible Implants

One key obstacle in employing silicon integrated circuits in flexible implants is ensuring a long-term operation of the chip within the wet corrosive environment of the body. For this reason, throughout the years, various biocompatible insulating …

11nW Signal Acquisition Platform for Remote Biosensing

This paper presents the design of an extremely low-energy biosensing platform that utilizes voltage to time conversion and time-mode signal processing to sense and accommodate electrophysiological biosignals that will be later sent remotely using a …

An Energy-Efficient Multi-Sensor Compressed Sensing System Employing Time-Mode Signal Processing Techniques

This paper presents the design of an ultra-low energy, rakeness-based compressed sensing (CS) system that utilizes time-mode (TM) signal processing (TMSP). To realize TM CS operation, the presented implementation makes use of monostable multivibrator …

An Asynchronous Pipelined Time-to-Digital Converter Using Time-Domain Subtraction

This paper presents the design of a low-power asynchronous pipelined time-to-digital converter (AP-TDC) to be employed in a time-domain signal processing system. The presented AP-TDC utilizes two novel concepts, namely time-domain subtraction and …

Design Exploration of a 65nm Sub-VT CMOS Digital Decimation Filter Chain

This paper presents an analysis on energy dissipation of digital half-band filters operating in the sub-threshold (sub-VT) region with throughput and supply voltage constraints. A 12-bit filter is implemented along with various unfolded structures, …

Ultra Low Energy vs Throughput Design Exploration of 65 nm Sub-VT CMOS Digital Filters

This paper presents an analysis on energy dissipation of a digital half band filters operated in the the sub-threshold (sub-VT ) region with throughput constraints. The degradation of speed in the sub-VT domain is counteracted by unfolding the …

A < 1 pJ Sub-VT Cardiac Event Detector in 65 nm LL-HVT CMOS

This paper presents the hardware implementation of a wavelet based event detector for cardiac pacemakers. A high level energy estimation flow was applied to evaluate energy efficiency of standard-cell based designs, over several CMOS technology …

Minimum-Energy Sub-Threshold Self-Timed Circuits: Design Methodology and a Case Study

This paper addresses the design of self-timed energy-minimum circuits, operating in the sub-VT domain. The paper presents a generic implementation template using bundled-data circuitry and current sensing completion detection. To support this, a …