Ultra Low Energy vs Throughput Design Exploration of 65 nm Sub-VT CMOS Digital Filters

Abstract

This paper presents an analysis on energy dissipation of a digital half band filters operated in the the sub-threshold (sub-VT ) region with throughput constraints. The degradation of speed in the sub-VT domain is counteracted by unfolding the architectures. A filter is implemented in a basic 12-bit and its various unfolded structures. The designs are synthesized in a 65 nm low-leakage high-threshold CMOS technology. A sub-VT energy model is applied to characterize the designs in the sub-VT domain. The results from application of an energy model shows that the unfolded by 2 architecture is most energy efficient, dissipating 22% less energy compared to it the original filter implementation at energy minimum voltage. Unfolded by 4 architecture, however, is the best for throughput requirements of around 120Ksamples/sec to 1Msamples/s, as it dissipates less energy than any other implementation in this speed range.

Publication
In Proceedigs of NORCHIP 2010
Date

Bibtex

@inproceedings{sheraziNorchip2010,
  author = {Sherazi, S.M.Y. and Rodrigues, J.N. and Akgun, O. C. and Sjöland, H. and Nilsson, P.},
  booktitle = {Proceedings of NORCHIP},
  title = {{Ultra Low Energy vs Throughput Design Exploration of 65 nm Sub-VT CMOS Digital Filters}},
  year = {2010},
  pages = {1--4},
  doi = {10.1109/NORCHIP.2010.5669452}
}