Design Exploration of a 65nm Sub-VT CMOS Digital Decimation Filter Chain


This paper presents an analysis on energy dissipation of digital half-band filters operating in the sub-threshold (sub-VT) region with throughput and supply voltage constraints. A 12-bit filter is implemented along with various unfolded structures, used to form a decimation filter chain. The designs are synthesized in a 65 nm low-leakage CMOS technology with various threshold voltages. A sub-VT energy model is applied to characterize the designs in the sub-VT domain. The results show that the low-leakage standard-threshold technology is suitable for the required throughput range between 250 Ksamples/s and 2 Msamples/s, at a supply voltage of 260 mV. The total energy dissipation of the filter is 205 fJ per sample.

In Proceedings of 2011 IEEE International Symposium on Circuits and Systems


  author = {Sherazi, S. M. Yasser and Nilsson, Peter and Akgun, O. C. and Sjoland, H. and Rodrigues, J. N.},
  booktitle = {Proceedings of 2011 IEEE International Symposium on Circuits and Systems (ISCAS)},
  title = {{Design Exploration of a 65 nm Sub-VT CMOS digital decimation filter chain}},
  year = {2011},
  pages = {837--840},
  doi = {10.1109/ISCAS.2011.5937696}