An Asynchronous Pipelined Time-to-Digital Converter Using Time-Domain Subtraction

Abstract

This paper presents the design of a low-power asynchronous pipelined time-to-digital converter (AP-TDC) to be employed in a time-domain signal processing system. The presented AP-TDC utilizes two novel concepts, namely time-domain subtraction and absolute value based algorithmic conversion. The design and simulation of the AP-TDC is done using a standard CMOS 65 nm process. The least-significant-bit resolution of the AP-TDC is designed to be 200 ps and the AP-TDC outputs 7-bit digital words with an ENOB of 6.2 bits. The dynamic range of the TDC is 25.4 ns and the TDC core consumes 38 μW from a supply voltage of 1V and has a total area of 1275 μm2. When compared to a Flash TDC implementation using the same delay elements, power consumption, total area, and conversion time are reduced by 28.3%, 31.5%, and 24.6%, respectively. The AP-TDC has a figure-of-merit of 9.9-fJ/conversion step.

Publication
In Proceedings of IEEE International Symposium on Circuits and Systems
Date

Bibtex

@inproceedings{akgunISCAS2018,
  author = {Akgun, O. C.},
  booktitle = {Proceedings of IEEE International Symposium on Circuits and Systems (ISCAS)},
  title = {{"An Asynchronous Pipelined Time-to-Digital Converter Using Time-Domain Subtraction"}},
  month = {May}, 
  year = {2018},
  pages = {1-5},
  doi = {10.1109/ISCAS.2018.8351554}
}