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This manuscript presents the digital hardware realization of a wavelet based event detector for cardiac pacemaker applications. The architecture of the detector is partially folded to minimize hardware cost. An energy model is applied to evaluate the …

This paper describes the implementation of a 12-bit 230 MS/s pipelined ADC using a conventional 1.8 V, 0.18 mum digital CMOS process.

In this paper a novel completion detection method for self-timed, asynchronous subthreshold circuits is presented. By employing the self-timed operation principle, substantial speed gains in the operation of the asynchronous pipelines can be …

In this paper implementation of a novel completion detection method for self-timed, asynchronous subthreshold circuits is presented. By employing the self-timed operation principle, substantial speed gains in the operation of the asynchronous …

In this paper the advantages of using differential cascode voltage switch pass gate (DCVSPG) logic with regard to standard CMOS for subthreshold operation are presented. The two families are compared in terms of their performance and …

A novel active-RC biquad is presented which can be reconfigured as a polyphase filter for a low IF wireless receiver architecture, and as a lowpass filter for a zero IF wireless receiver architecture. A second order lowpass-polyphase reconfigurable …