Energy Dissipation Reduction of a Cardiac Event Detector in the Sub-VT Domain By Architectural Folding

Abstract

This manuscript presents the digital hardware realization of a wavelet based event detector for cardiac pacemaker applications. The architecture of the detector is partially folded to minimize hardware cost. An energy model is applied to evaluate the energy efficiency in the sub-threshold (sub-VT) domain. The design is synthesized in 65 nm low leakage-high threshold CMOS technology, and it is shown that folding reduces the area cost by 30.6%. Folding decreases energy dissipation of the circuit by 14.4% in the sub-VT regime, where the circuit dissipates 3.3 pJ per sample at VDD=0.26 V.

Publication
In Lecture Notes in Computer Science, Integrated Circuit and System Design, Power and Timing Modeling, Optimization and Simulation
Date

Bibtex

@incollection{jrs2009patmos,
  author = {Rodrigues, J. and Akgun, O. C. and Acharya, P. and de la Calle, A. and Leblebici, Y. and {\"O}wall, V.},
  title = {{Energy Dissipation Reduction of a Cardiac Event Detector in the Sub-VT Domain By Architectural Folding}},
  booktitle = {Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation},
  series = {Lecture Notes in Computer Science},
  pages = {347-356},
  volume = {5953},
  doi = {10.1007/978-3-642-11802-9_39},
  year = {2010}
}