Weak Inversion Performance of CMOS and DCVSPG Logic Families in Sub-300 mV Range

Abstract

In this paper the advantages of using differential cascode voltage switch pass gate (DCVSPG) logic with regard to standard CMOS for subthreshold operation are presented. The two families are compared in terms of their performance and energy-delay-product (EDP) figures. Multiple gates were simulated using 0.18 mum standard CMOS technology. Simulation results show that DCVSPG NAND2 gate has 71%, DCVSPG NOR2 gate has 82% and DCVSPG full adder has 66% EDP savings over the CMOS counterparts.

Publication
In Proceedings of IEEE International Symposium on Circuits and Systems
Date

Bibtex

@inproceedings{akgunISCAS2006,
  author = {Akgun, O. C. and Leblebici, Y.},
  booktitle = {Proceedings of IEEE International Symposium on Circuits and Systems (ISCAS)},
  title = {{Weak Inversion Performance of CMOS and DCVSPG Logic Families in Sub-300 mV Range}},
  year = {2006},
  pages = {1251-1254},
  doi = {10.1109/ISCAS.2006.1692819}
}