Design Approaches for Low-Power Reconfigurable Analog-to-Digital Converters


With the recent advancements in integrated circuit technology, digital CMOS circuits have been exponentially scaled according to Moore’s Law over the last three decades. Because analog circuits cannot be scaled down as easy as the digital circuits, it’s desirable to minimize analog signal processing in any integrated system. Also with developments in digital signal processing algorithms and development tools, digital signal processing has been the preferred choice of signal processing in terms of development costs and ease of implementation. To move the signal processing from the analog domain to digital domain, analog-to-digital converters are required. To achieve lower manufacturing costs, it is desirable to have systems that can realize multiple functions or that can support multiple standards on a single chip. These kinds of systems save expensive die area and also save board space which are two qualities that are highly desired in terms of cost. For multi-function or multi-standard applications, pipelined ADCs can be used and they can be easily reconfigured in terms of resolution. However it is not easy to reconfigure pipelined ADCs for power-scaled operation. Objective of this thesis is to investigate design approaches for reconfigurable ADCs with the linear power-speed scaling feature. Reconfigurable low-power ADC designs are useful in mixed-signal systems where the power consumption is an issue, like multi-standard wireless handsets and portable digital video applications. The reconfigurable architecture proposed in this thesis achieves the desired feature of scaling power linearly with speed. The basic pipelined ADC is reconfigured as a cascade of cyclic ADC stages to achieve power-speed scaling. A novel Capacitor Reuse Technique is also proposed to minimize the amount of additional hardware to realize the reconfigurable operation.

MSc Thesis