Digital circuits operating in the sub-threshold regime are able to perform minimum energy operation at a given delay. In the sub-threshold regime the circuit delay, and hence, the leakage energy consumption depend on the supply voltage exponentially. By reducing the idle time of the circuit, the energy-minimum supply voltage can be reduced, resulting in lower energy consumption. This paper first presents an energy model for comparing synchronous and asynchronous sub-threshold operation. After the presentation of the model, design and simulation results of a novel current sensing based completion detection circuit that is applicable to coarse-grained single-rail asynchronous pipelines working in the sub-threshold regime is shown. The system works by sensing the changes in the current consumption of static CMOS combinational blocks and generates completion signals delayed in proportion to the computation taking place. The method is applied as a proof of concept to the operation of a static CMOS 16-bit adder logic block that has been designed using conventional EDA tools for a 0.18 µm CMOS process. When operating with a supply voltage of 220 mV, speed improvements of up to 19.3% have been observed in the operation of the circuit. If the system is operated at the asynchronous energy-minimum supply voltage, an energy consumption reduction of 17% can be realized for the same computation load.