Ultra Low Energy Design Exploration of Digital Decimation Filters in 65 nm Dual-VT CMOS in the Sub-VT Domain


This paper presents an analysis of energy dissipation of a decimation filter chain of four Half Band Digital (HBD) filters operated in the sub-threshold (sub-VT) region with throughput constraints. To combat speed degradation due to scaling of supply voltage, various HBD filters are implemented as unfolded structures. The designs are synthesized in 65 nm CMOS technology with low-power and three threshold options, both as single-VT and as dual-VT. A sub-VT energy model is applied to characterize the designs in the sub-VT domain. Simulation results show that the unfolded by two and four architectures are the most energy efficient for throughput requirements between 250 k samples/s, and 2 M samples/s. By the selection of optimum architectures and standard cells, at the required throughput the simulated minimum energy dissipation for the required throughput per output sample is 164 fJ and 205 fJ, with single supply voltage of 260 mV.

In Microprocessors and Microsystems