Energy-minimum Sub-threshold Self-Timed Circuits Using Current-Sensing Completion Detection


This study addresses the design of self-timed energy-minimum circuits, operating in the sub-VT domain and a generic implementation template using bundled-data circuitry and current sensing completion detection (CSCD). Furthermore, a fully decoupled latch controller was developed, which integrates with the current-sensing circuitry. Different configurations that utilise the proposed latch controller are highlighted. A contemporary synchronous electronic design automation tools-based design flow, which transforms a synchronous design into a corresponding self-timed circuit, is outlined. Different use cases of the CSCD system are examined. The design flow and the current-sensing technique are validated by the implementation of a self-timed version of a wavelet-based event detector for cardiac pacemaker applications in a standard 65 nm CMOS process. The chip was fabricated and verified to operate down to 250 mV. Spice simulations indicate a gain of 52.58 in throughput because of asynchronous operation. By trading the throughput improvement, energy dissipation is reduced by 16.8 at the energy-minimum supply voltage.

In IET Computers & Digital Techniques


  author = {O.C. Akgun and J.N. Rodrigues and J. Spars\o},
  collaboration = {},
  title = {Energy-Minimum Sub-Threshold Self-Timed Circuits Using Current-Sensing Completion Detection},
  publisher = {IET},
  year = {2011},
  journal = {IET Computers \& Digital Techniques},
  volume = {5},
  number = {4},
  pages = {342-353},
  doi = {10.1049/iet-cdt.2010.0118}