A < 1 pJ Sub-VT Cardiac Event Detector in 65 nm LL-HVT CMOS

Abstract

This paper presents the hardware implementation of a wavelet based event detector for cardiac pacemakers. A high level energy estimation flow was applied to evaluate energy efficiency of standard-cell based designs, over several CMOS technology generations, from 180 to 65 nm, operated in the sub-threshold domain. The simulation results indicate a 65 nm low-leakage high-threshold (LL-HVT) CMOS technology as the favourable choice. Accordingly, the design was fabricated in 65nm LL-HVT CMOS. Measurements validate the simulation results and prove that the circuit is fully functional down to a supply voltage of 250mV. At the energy minimum voltage of 320mV the circuit dissipates 0.88 pJ per sample at a clock rate of 20 kHz.

Publication
In Proceedings of 18th IEEE/IFIP International Conference on Very Large Scale Integration of System-on-Chip
Date

Bibtex

@inproceedings{jrsVLSISoc2010,
  author = {Rodrigues, J. N. and Akgun, O. C. and {\"O}wall, V.},
  title = {{A $<$ 1 pJ sub-VT cardiac event detector in 65 nm LL-HVT
               CMOS}},
  booktitle = {18th IEEE/IFIP International
               Conference on Very Large Scale Integration of System-on-Chip (VLSI-SoC),
               Spain},
  year = {2010},
  pages = {253--258},
  doi = {10.1109/VLSISOC.2010.5642669}
}