Selected Publications

This paper presents the design of a low-power asynchronous pipelined time-to-digital converter (AP-TDC) to be employed in a time-domain signal processing system. The presented AP-TDC utilizes two novel concepts, namely time-domain subtraction and absolute value based algorithmic conversion. When compared to a Flash TDC implementation using the same delay elements, power consumption, total area, and conversion time are reduced by 28.3%, 31.5%, and 24.6%, respectively.
In ISCAS 2018

This paper presents a flow that is suitable to estimate energy dissipation of digital standard-cell based designs which are determined to operate in the subthreshold regime. The flow is applicable on gate-level netlists, where back-annotated toggle information is used to find the minimum energy operation point, corresponding maximum clock frequency, as well as the dissipated energy per clock cycle.
In IEEE TBIOCAS, February 2012

This study addresses the design of self-timed energy-minimum circuits, operating in the sub-VT domain and a generic implementation template using bundled-data circuitry and current sensing completion detection (CSCD).
In IET Computers & Digital Techniques, November 2011

This paper first presents an energy model for comparing synchronous and asynchronous sub-threshold operation. After the presentation of the model, design and simulation results of a novel current sensing based completion detection circuit that is applicable to coarse-grained single-rail asynchronous pipelines working in the sub-threshold regime is shown. The system works by sensing the changes in the current consumption of static CMOS combinational blocks and generates completion signals delayed in proportion to the computation taking place.
In International Journal of Circuit Theory and Applications, March 2009

This paper presents an in-depth comparison of synchronous and asynchronous techniques in the sub-threshold operating regime for their energy efficiency. From our analysis and simulations we have found out that asynchronous operation in the sub-threshold regime significantly lowers the supply voltage value that realizes the minimum energy operation and operating the digital circuits at a lower supply voltage value result in lower energy operation.
In JOLPE, December 2008

Recent Publications

More Publications

  • An Asynchronous Pipelined Time-to-Digital Converter Using Time-Domain Subtraction
    In ISCAS 2018

    Details PDF DOI BIBTEX

  • Ultra Low Energy Design Exploration of Digital Decimation Filters in 65 nm Dual-VT CMOS in the Sub-VT Domain
    In Microprocessors and Microsystems, December 2013

    Details DOI BIBTEX

  • High-Level Energy Estimation in the Sub-VT Domain: Simulation and Measurement of a Cardiac Event Detector
    In IEEE TBIOCAS, February 2012

    Details PDF DOI BIBTEX

  • Energy-minimum Sub-threshold Self-Timed Circuits Using Current-Sensing Completion Detection
    In IET Computers & Digital Techniques, November 2011

    Details PDF DOI BIBTEX

  • Design Exploration of a 65nm Sub-VT CMOS Digital Decimation Filter Chain
    In Proceedigs of ISCAS 2011

    Details PDF DOI BIBTEX

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